Description

¡EExcellent compatibility with different AMB.
¡EProvides advanced performance for next-generation severs.
¡EAll signals - clock, address, command,and data are buffered by high-speed Advanced Memory Buffer (AMB).
¡EApplies a Point-to-Point connection on the bus, serial signaling similar to PCI-Express.
¡EAllows increased bus speed with shorter connection path.
¡EGreatly improves the maximum number of DIMMs - up to eight 2-rank DIMMs.
¡EDaisy-Chain interconnection, AMB (buffer) to AMB, AMB to DRAM.
¡ESupport the MEMBIST, IBIST, and Design-for-Test functions.
¡EFail-over mechanism to map out bad bit lanes.
¡ECRC and ECC data protection.

By comparison, existing standard Registered DIMMs have a stub-bus architecture along the memory bus between each DIMM and the memory controller. As the memory operating frequency increases, the controller must reduce the number of DIMMs loaded on the memory bus to secure the signal quality and the signal timing margin along the critical path between the DRAM devices on the modules and the controller on the motherboard. This has presented the major bottleneck in achieving high performance in server application.